As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit. Very large scale integration (VLSI) techniques have continually evolved to meet the increasing demand. All aspects of the integrated circuit must be scaled down to fully minimize the device dimensions of the integrated circuit. In addition to minimizing transistor dimensions, one must minimize the dimensions of the electrical interconnections, which integrate the semiconductor devices, such as transistors, together on a microchip in order to form a complete circuit.
Currently, aluminum alloys are the most commonly used conductive materials for electrical interconnections in a VLSI integrated circuit. Aluminum and its alloys have been fully characterized for use as electrical interconnections, and much technology has been developed to aid in the formation of aluminum interconnections. While aluminum has very attractive features for use as an electrical interconnection such as low electrical resistivity and strong adhesion to silicon dioxide (SiO.sub.2), as VLSI dimensions reach into the deep-submicron Ultra Large Scale Integration (ULSI) regime, the deficiencies of aluminum and its alloys become limiting factors in achieving superior performance. For example, as the width of electrical interconnections becomes narrower, the resistance of aluminum becomes non-negligible and begins to contribute significantly to the resistance-capacitance (RC) time delay of the circuit. Additionally, with decreasing dimensions, design rules become increasingly restricted by aluminum interconnection reliability concerns such as electromigration, stress-induced void formation, hillock suppression, and current density limitations.
For these reasons, the microelectronics industry has recently migrated towards the investigation of more robust, more conductive metals for use in interconnection technology such as Copper (Cu). Cu is approximately 40% lower in resistivity than Al and has fewer reliability concerns such as electromigration.
However, a disadvantage in the use of Cu and its alloys for interconnection applications is that a manufacturable dry-etch process has not been demonstrated that can pattern Cu-based materials using standard photolithographic techniques. Therefore, to implement the use of Cu as a microelectronic interconnection material it has become necessary to develop alternate patterning techniques.
One technique is known as damascene. In damascene, a dielectric layer is deposited onto a substrate, patterned, and etched back such that grooves, vias, and other recessed regions etched into the dielectric layer represent the desired metal interconnection pattern. A conductive metal is then deposited over the entire surface of the device, filling the recessed regions and blanketing the surface of the dielectric layer. Next, the conductive material is polished back to a degree such that the conductive material becomes electrically isolated within the recessed regions etched out of the dielectric material.
An inadequately filled recessed region in a damascene process flow leads to the creation of a void or tunnel. Voids significantly degrade semiconductor device yields thereby adding to the total manufacturing cost. Gaps and void can cause significant problems in a semiconductor manufacturing process and are considerable issues for sputtered and evaporated films. One problem with gaps and voids is that they can trap impurities, such as etchant chemicals, which can harm the semiconductor device in subsequent process steps. Trapped impurities may then contaminate the semiconductor device which could degrade reliability. Trapped etchant chemicals may also continue to etch the electrical interconnection resulting in the thinning of electrical interconnections or the creation of a electrical open, thereby resulting in a failure. Interconnection thinning may lead to reliability problems such as electromigration and current-carrying limitations. Additionally, trapped contaminates may expand upon subjecting the semiconductor substrate to subsequent high temperature processing steps. Such expansion could cause significant damage to adjoining surface features of the semiconductor device. Finally, trapped contaminants may escape during a subsequent process step conducted within a process chamber, thereby contaminating all other semiconductor devices within the chamber.
The potential for forming voids is greatly increased by attempting to fill grooves of significantly varying widths together on a single substrate at the same interconnection level using deposition processes with relatively high sticking coefficients. This is because these deposition processes are typically optimized to fill a groove of a particular width. While such optimization techniques may be suitably employed to fill interconnections of this particular width on a semiconductor substrate, the problem is that grooves of widths for which the process has not been optimized run a much higher risk of void formation. This makes interconnection technology dependent on individual device layout. Such dependence degrades the manufacturability of such processes.
It is currently more desirable to form copper interconnections on a semiconductor substrate by Cu sputtering rather than by CVD of Cu. One reason why Cu sputtering is more desirable is that there is a significant cost associated with performing CVD of Cu. Equipment necessary to form CVD Cu layers is currently under development and not yet readily available for high production manufacturing environments. Additionally, the materials necessary to deposit CVD Cu layers are expensive, still under investigation, and the films are not likely to be very pure. Therefore, CVD of Cu is expensive and considerably adds to the total manufacturing cost of a semiconductor device. Furthermore, while some CVD techniques which exhibit low sticking coefficients may be capable of minimizing void formation, seams are still formed along the center of the CVD layers within the grooves. Seams are formed when deposited materials on laterally opposing walls within a groove grow into each other. These seams may be undesirable due to, for example, their negative impact on the grain size of the conductive layer and their susceptibility to trapping impurities. Finally, CVD techniques which exhibit low sticking coefficients also exhibit low deposition rates. Therefore, in the interest of manufacturability, higher sticking coefficient CVD processes are typically used to accelerate throughput time. However, these higher sticking coefficient CVD processes exhibit the same short-comings as the high sticking coefficient processes discussed above.
Existing sputter deposition (PVD) systems can easily and cheaply deposit Cu layers. However, sputter deposition systems have exhibited significant limitations in their ability to fill recessed regions in a damascene process flow as discussed above. Grooves, openings, etc. with aspect ratios below 0.5 are generally adequately filled without the aid of a reflow process. However, the reflow process additionally serves to improve the step coverage and general film quality of these wide lines. High aspect ratio openings, on the other hand, do require a reflow step to eliminate gaps and voids within the copper layer. These limitations have restricted the applicability of sputter deposition systems in a damascene process.
Another disadvantage of copper metallization is that reaction and interdiffusion between Cu in the metallization film and Si included in the substrate, or Cu in the metallization film and Si in the insulating film occur during a heat treating process such as annealing or reflow steps. This is because the Cu metallization film is directly in contact with the Si substrate at the through holes in the insulating film. Reaction and interdiffusion cause an increase in the contact resistance and degradation of the Cu metallization. In addition, Cu in the silicon substrate also decreases minority carrier lifetimes which degrade the performance of the chip. For these reasons, barrier layers have been used to prevent the reaction and interdiffusion between Cu and Si. For example, U.S. Pat. No. 4,985,750 describes the use of titanium nitride (TiN), tungsten (W), tungsten nitride (WN), zirconium nitride (ZrN), titanium carbide (TiC), tungsten carbide (WC), tantalum (Ta), tantalum nitride (TaN) or titanium tungsten (TiW) barrier layers for copper.
However, these barrier layers exhibit instability at the higher temperatures (&gt;500.degree. C.) required to reflow copper into the trench for damascene. A reflow step, which is necessary when filling high aspect ratio openings, is a process step in which a conductive layer is exposed to an elevated temperature under vacuum for a period of time necessary to cause the conductive layer to "smooth out" and substantially seal gaps in the conductive material.
In order to overcome this limitation, certain materials have been deposited prior to deposition of copper which act as wetting agents. These agents serve to wet the copper layer in the opening by providing the copper layer with a low interfacial energy within the opening. For example, U.S. Pat. No. 5,654,232 describes the use of a silicon nitride or tantalum wetting layer to prevent copper from agglomerating out of an opening during a subsequent reflow step. It is thought that the driving force for the reflow of the copper layer into the opening is the minimization in surface free energy in combination with sidewalls comprising these wetting layers. These wetting layers are thought to provide the copper layer with a low interfacial energy within the opening and to actually physically draw the copper layer into the opening.
Therefore, in the fabrication of silicon substrates, there exists a need for improved methods of filling openings, including high aspect ratio openings. More particularly, there exists a need for a barrier layer which is stable to the high temperatures required to reflow copper after PVD deposition, and there exists a need for a wetting layer which effectively lowers the temperature at which the copper reflows and therefore, allows the use of typical barrier layers.